Power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are commonly used in RF applications such as transmitters and receivers and other products such as plasma generators. For such applications, it is desirable that power MOSFET devices consistently strive to provide higher performance and higher frequency operation.
The performance of a power MOSFET device is closely related to its gate dimensions. A smaller gate has a shorter channel dimension than does a larger gate and the shorter channel dimension of a smaller gate contributes to high gain and efficiency of the device at high frequencies. Power output is directly proportional to the gate periphery. In addition to the channel dimensions of the gate, device performance of a power MOSFET at radio frequencies is also closely related to the capacitances of the device. First, the input capacitance of the MOSFET, referred to as C.sub.iss, composed of gate capacitances C.sub.gs and C.sub.gd, is critical to transistor performance. Input capacitance C.sub.iss is inversely proportional to the maximum frequency of the device, F.sub.max and hence F.sub.t. Thus, reducing C.sub.iss has the effect of increasing the maximum frequency at which the MOSFET can operate as well as the device gain and efficiency. It is therefore desirable to decrease C.sub.gs and/or C.sub.gd in order to reduce C.sub.iss. Conversely, it is undesirable to increase either C.sub.gs and C.sub.gd to the extent that C.sub.iss would be increased, for this would have the undesirable effect of producing a corresponding decrease in F.sub.t. As is well known in the art, C.sub.gs is the gate to source capacitance of the device and C.sub.gd is the gate to drain capacitance of the device.
Second, the feedback capacitance of the MOSFET, referred to as C.sub.rss, is the capacitance from the output to the input of the device and is therefore equal to gate to drain capacitance C.sub.gd only. The value of C.sub.rss is voltage dependent and is a critical dimension in the design of any power MOSFET application that uses negative feedback to obtain wide band performance.
Vertical, double diffused MOS (VDMOS) devices and in particular TMOS devices, are characterized as having two channel regions under the gate in order to increase the gate periphery to attain higher packaging density so that a higher power per unit area of the device may be achieved. The term "vertical" is descriptive of the fact that currents flow in the vertical direction of the transistor cell. The two channels are separated by an area of a drain under the gate that determines the value of C.sub.gd. C.sub.gd will obviously be decreased by decreasing the portion of the drain under the gate, but this will also serve to increase the drain resistance of the device, thereby degrading device performance, more specifically power and gain. Otherwise altering the drain region under the gate may have other, undesirable effects. For instance, increasing the doping of the drain region under the gate will lower the breakdown voltage of the device.
A typical structure of a prior art vertical MOSFET that utilizes polysilicon as part of the gate region is shown in FIG. 1. FIG. 1 is the prior art FIG. 1 of European patent application 84100812.5, bearing publication number 0119400, was published on Sep. 25, 1984, hereby incorporated by reference. An N--type layer of low impurity concentration is epitaxially grown on low resistivity drain substrate 1 having an N+-type silicon wafer of high impurity concentration to form drain region 2 of high resistivity. Semiconductor wafer 4 is composed of drain substrate 1 together with drain region 2. Next, insulating coating 3 for a gate is formed on a top surface of drain region 2 by thermal oxidation, followed by a polysilicon film that forms gate electrode 5. Portions of the polysilicon film are selectively removed using photo-etching to open source windows. Using a double diffusion method, through the source windows thus formed, well region 6 that operates as a channel is formed. Advantages of applying the double diffusion method to a large number of transistor elements, known in the art, include uniformity in the characteristics of each transistor, improved production yield, and small transistor size. Next, source and well contact regions 7, 8 which diffuse concentrically within well region 6 from the center outward are formed as shown. After completion of the double diffusion process, source electrode 10 is formed along the upper surface of the polysilicon gate electrode 5 through insulating film 9 by vacuum deposition. Finally, drain electrode 11 is formed on the bottom surface of drain substrate 1 as shown.
A problem with the prior art vertical MOSFET of FIG. 1 has to do with the formation of the gate electrode 5 with respect to the drain region 2 and the large gate to drain capacitance C.sub.gd that results. Referring again to FIG. 1, it can be seen that these regions are separated only by the thin layer of insulating coating 3, resulting in a large capacitance between the gate and drain regions. The European patent application 84100812.5 is most concerned with high switching speeds and the feedback function that the large C.sub.gd will serve from the output of a switching element to its input. The presence of this feedback function introduced by C.sub.gd makes it difficult to perform switching at high speeds. Therefore, European patent application 84100812.5, while not concerned with RF power MOSFET device applications, is nonetheless concerned with lowering C.sub.gd.
European patent application 84100812.5 addresses the large C.sub.gd problem by interposing a raised portion of oxide film between the drain region 2 and the polysilicon gate electrode 5. An enlarged portion of oxide film interposed between the drain and gate regions projects up from the drain region towards the gate and has the effect of increasing the distance between gate and drain and therefore decreasing C.sub.gd. The three embodiments in which an enlarged portion of oxide film is interposed between the drain and gate regions are illustrated in FIGS. 2(I), 3(G), and 4(H), respectively, of the 84100812.5 application.
While the enlarged portion of oxide film does operate to reduce C.sub.gd, the process required to form the enlarged portion of oxide film requires additional steps directed just to its formation, rendering the process more lengthy. In the first embodiment, shown in FIG. 2(I), it is necessary to form recess portions into which the enlarged portions of oxide film 23 are formed. The enlarged portions of oxide film are in addition to the film of silicon oxide film that is normally disposed between the gate and drain regions. In the second embodiment, shown in FIG. 3(G), thick oxide regions 125 are formed, a silicon nitride film and underlying thin oxide film removed, and then the silicon oxide insulating layer that normally exists between the gate and drain is formed. As in FIG. 2(I), thick oxide regions 125 have the effect of pushing up the peripheral portion of film 123 in order to maximize the distance between the gate and drain. Finally, in the third embodiment, shown in FIG. 4(H), the enlarged oxide bump 226 is formed by actually oxidizing a portion of polysilicon gate electrode 223.
In addition to requiring a complicated manufacturing process to form the enlarged oxide bumps, European patent application 84100812.5 has a most undesirable side effect. As shown in FIGS. 2(I), 3(G), and 4(H), the last step of forming the MOSFET device is to form the source electrode over the polysilicon portions of the gate; the gate electrode itself is not shown. The formation of the source electrode over the entire gate region, however, operates to dramatically increase the gate to source capacitance, C.sub.gs, of the device.
Such a substantial increase in C.sub.gs of the device may not be of concern in the high speed switching technology to which the European patent application 84100812.5, but it cannot be tolerated in RF applications that use power MOSFET devices to which the present invention is directed. As discussed above, the input capacitance of the MOSFET, C.sub.iss, is inversely proportional to F.sub.t and is therefore a critical parameter of power MOSFET performance. Since C.sub.iss is composed of both gate capacitances C.sub.gs and C.sub.gd, an increase in either C.sub.gs or C.sub.gd that operates to increase C.sub.iss will have an adverse effect on power MOSFET device performance. Since the source electrode of the European patent application 84100812.5 operates to substantially increase C.sub.gs, this is not an acceptable solution for use with power MOSFET devices.
Referring to FIG. 2, another structure of a typical prior art vertical MOSFET is shown. One of the most important distinctions between FIG. 1 and FIG. 2 is that the structure of FIG. 2 does not utilize polysilicon as part of the gate region; rather gate 34 is formed by gate oxide 36 and metal gate electrode 38. FIG. 2 is the prior art FIG. 1 of U.S. Pat. No. 4,455,565, issued on Jun. 19, 1984 to Goodman et al., hereby incorporated by reference. In the figure, the following parts of the MOSFET structure are shown: substrate 12, 14--first surface of substrate 12,16--second surface of substrate 12, source region 18, body region 20, drain region 22, body/drain P/N junction 23, 24--high conductivity portion of drain region 22, 26--extended drain/region of lower conductivity portion of 22, channel portions 28, drain electrode 30, source electrode 32, and gate region 34 composed of gate oxide 36 and gate electrode 38.
As described in U.S. Pat. No. 4,455,565 at column 2, lines 9 to 37, adjacent source, body and drain regions 18, 20, and 22, respectively, are of alternate conductivity type. For instance, source region 18 is N+, body region 20 is P, and drain region 22 is N+. Drain electrode 30 along the bottom surface 16 of substrate 12 in contact with 24, the relatively high conductivity portion of the drain region 22. Source electrode 32 is in contact with source regions 18 and body regions 20 in areas displaced from channel portions 28. As shown in the figure, gate 34 is disposed on surface 14 over both pair of channel portions 28 and extended drain region 26 between channel portions 28. Gate 34 includes gate oxide 36 over the first surface 14 of substrate 12 and gate electrode 38 formed on gate oxide 36 as shown.
U.S. Pat. No. 4,455,565, like European patent application 84100812.5, is concerned with the gate to drain capacitance C.sub.gd but reduces C.sub.gd using a different vertical MOSFET method and structure. In the invention of U.S. Pat. No. 4,455,565, illustrated in FIG. 2 of the patent, the portion of gate electrode 38 that overlays the extended drain region 26 disposed between the two channel portions 28 is removed and replaced with an insulated shield electrode. The portions of gate electrode 38 that overlay the channel portions 28 and source regions 28 are maintained. The effect is two gate electrodes separated by an insulated shield electrode that overlays the drain region of the device. This operates to minimize the feedback capacitance by applying a substantially high positive bias and therefore has the desirable effect of decreasing gate to drain capacitance C.sub.gd.
While this configuration does operate to lower gate to drain capacitance, it is not accomplished without considerable cost. The insulated shield electrode must be maintained at a constant positive bias. Additional circuitry is required to maintain the insulated shield electrode at the constant bias voltage by applying a voltage, usually much larger than the voltage applied to the gate electrodes, to the insulated shield electrode. Column 3, lines 35-39, of the patent disclose that while the gate electrode may be provided with 0 to 30 volts, the insulated gate electrode would be provided with 30 to 60 volts in order to maintain the required constant bias voltage. Thus, even though U.S. Pat. No. 4,455,565 does operate to reduce C.sub.gd, the additional circuitry required to maintain the insulated shield electrode that makes it possible to achieve the reduced C.sub.gd is a definite drawback.
There is therefore an unmet need in the art to be able to reduce the gate to drain capacitance of a MOS transistor device without otherwise adversely affecting the performance of the device or requiring additional circuitry or processing steps that significantly increase manufacturing costs of the device.